In copper (Cu) Damascene processes, metal tracks and contacts are lined with a Cu diffusion barrier prior to the metalization in the BEOL (Back End of Line process).
Porous low-k materials (LK materials) are increasingly also being integrated as ILDs (Interlayer Dielectrics) instead of silicon dioxide. In the event of plasma etching into these materials, the pores at the sidewalls of the etched recesses are partially uncovered, so that when the diffusion barrier is being applied, typically by means of PVD or the like, discontinuities may form in the diffusion barrier as a result of large pores. To fill these pores, the sidewalls can be wetted by means of self-aligned molecules (SAMs), and then the diffusion barrier can be deposited.
Examples of low-k materials of this type include carbon-doped silicon dioxide, other silicon-containing materials and carbon-containing compounds. Exceptions in this context include, for example, SiLK™ (LK: low-k material with a low dielectric constant) and porous p-SiLK™ and fluorinated hydrocarbons.
These materials are applied to the substrate as separating layers between the metallization levels during chip production, after which recesses are then etched into this material. These recesses are ultimately filled with a metal, generally copper, so that metal interconnects (metal trenches) are formed. The metalization levels are also connected to one another by contacts, by particularly deep vias being etched through the ILD as far as the next metallization level down, these vias then likewise are filled with a metal. This process is also known as the dual Damascene process.
In the case of the low-k materials, recesses are formed in the surface of the trenches or vias during the plasma etching, and at the same time large pores in the low-k material may also be uncovered. It is also possible for individual pores to become connected to one another during further processing steps, such as etching, so as to form even larger cavities.
In particular the pores close to surfaces are exposed to various chemical substances, such as water, water vapor or the like, during chip production, and may form even larger cavities as a result of individual pores being linked to one another through channels. As a result, the dielectric properties of the ILDs are adversely affected or even completely destroyed.
To prevent this, it is necessary for the pores to be sealed with a suitable material. In principle, the sealing can be effected using a CVD liner, on which a diffusion barrier is then deposited. However, the CVD process may cause the same “defects” as those described above.
A similar process is described in WO 01/54190 A1 (corresponding U.S. Patent Publication No. 2001/0051420 A1). However, as the scale of integration increases further, this process is reaching its limits, i.e., on account of the cumulatively considerable layer thicknesses of over 25 nm, it cannot be employed in narrow trenches.
Another possible way of sealing the large pores consists in using the above-described SAMs, which are provided with functional groups which on the one hand have an affinity for Si atoms (in the case of methyl-silsesquioxane materials (MSQ materials)) and on the other hand have a preferential affinity for metal atoms (e.g., barrier metals, also copper) (DE 102 27 663.3-14). Furthermore, the functional group, which is to be bonded to the metal, has the property of preventing oxidation of the metal, in this case copper. This makes it possible to prevent the formation of ions, which may be accelerated in the electric field, which can lead to leakage currents between adjacent metal tracks.
In this case, the SAMs are applied by means of dip coating or a spin-on process.